VGLUE命令在电子封装实例中出现的问题

liujihang029

祝效华 余志祥等编著《ANSYS高级工程有限元分析范例精选》 一书284页，第13章电子封装中的热模拟实例。

图中的黑点代表的是焊点，把书上的代码抄写下来，在运行的时候出现问题。下面一层的焊点SB3能够与PCB和SUB进行VGLUE操作，上面一层的焊点SB1和SB2与SUB和HS无法进行VGLUE操作。
问题是，两层焊点是用同一种方法生成的模型。
请哪位帮忙看看代码那里出问题了！多谢多谢！
代码如下：
FINISH
/CLE
/UNITS, SI
/FILNAME, MCM
/TITLE, 3D THERMAL SIMULATION OF MULTICHIIP MODULE
!!!设定结构基本参数
!定义中间芯片尺寸
*SET, D1_LENGTH, 8E-3
*SET, D1_WIDTH, 8E-3
*SET, D1_HEIGHT, 0.65E-3
!定义周围芯片尺寸
*SET, D2_LENGTH, 5E-3
*SET, D2_WIDTH, 5E-3
*SET, D2_HEIGHT, 0.65E-3
!定义中间芯片下凸点尺寸和数量
*SET, SB1_RADIUS, 0.15E-3
*SET, SB1_DIST, 0.75E-3
*SET, SB1_NB, 10
*SET, SB1_HEIGHT, 0.2E-3
*SET, SB1_SIDE, 0.625E-3
!定义周围芯片下凸点尺寸和数量
*SET, SB2_RADIUS, SB1_RADIUS
*SET, SB2_DIST, 0.75E-3
*SET, SB2_NB, 6
*SET, SB2_HEIGHT, 0.2E-3
*SET, SB2_SIDE, 0.625E-3
!定义基板尺寸
*SET, SUB_LENGTH, 40E-3
*SET, SUB_WIDTH, 40E-3
*SET, SUB_HEIGHT, 1.5E-3
!定义基板下焊球尺寸和数量
*SET, SB3_RADIUS, 0.3E-3
*SET, SB3_DIST, 1.27E-3
*SET, SB3_NB, 26
*SET, SB3_HEIGHT, 0.4E-3
*SET, SB3_SIDE, 4.125E-3
!定义中间芯片和周围芯片中心距
*SET, D_DIST, 11.5E-3
!定义PCB尺寸
*SET, PCB_LENGTH, 100E-3
*SET, PCB_WIDTH, 100E-3
*SET, PCB_HEIGHT, 1.5E-3
!定义扩展面的尺寸
*SET, HS_LENGTH, 40E-3
*SET, HS_WIDTH, 40E-3
*SET, HS_THICK, 1.5E-3
!定义粘结剂厚度
*SET, SA_HEIGHT, 0.15E-3
!定义热介质材料厚度
*SET, TIM_HEIGHT, 0.15E-3
!定义热沉尺寸
*SET, SINK_LENGTH, 46.5E-3
*SET, SINK_WIDTH, 46.5E-3
*SET, SINK_HEIGHT, 1.5E-3
*SET, FIN_NB, 16
*SET, FIN_HEIGHT, 8E-3
*SET, FIN_THICK, 1.5E-3
*SET, FIN_DIST, 1.5E-3

!!!选择单元类型
/PREP7

ET, 1, SOLID70

!!!定义材料参数
MP, KXX, 1, 82
MP, KXX, 2, 36
MP, KXX, 3, 0.2
MP, KXX, 4, 50
MP, KXX, 5, 8.37
MP, KYY, 5, 8.37
MP, KZZ, 5, 0.32
MP, KXX, 6, 390
MP, KXX, 7, 1.1
MP, KXX, 8, 1
MP, KXX, 9, 240

!!!建立几何模型

/PNUM, VOLU, 1
!BOPTN, KEEP, YES

!建立PCB模型
BLOCK, 0, PCB_LENGTH/2, 0, PCB_WIDTH/2, 0, PCB_HEIGHT

WPOFF, SB3_DIST/2, SB3_DIST/2, PCB_HEIGHT+SB3_HEIGHT/2
SPHERE, SB3_RADIUS, , 0, 360

WPOFF, -SB3_DIST/2, -SB3_DIST/2, SB3_HEIGHT/2
BLOCK, 0, SUB_LENGTH/2, 0, SUB_WIDTH/2, 0, SUB_HEIGHT

VOVLAP, ALL
NUMCMP, ALL

CSYS, 0
VSEL, S, LOC, Z, 0, PCB_HEIGHT
VADD, ALL

CSYS, 4
VSEL, S, LOC, Z, 0, SUB_HEIGHT
VADD, ALL

VSEL, S, LOC, Z, 0, -SB3_HEIGHT
VGEN, SB3_NB/2, ALL, , , SB3_DIST, , , , 0

VSEL, S, LOC, Z, 0, -SB3_HEIGHT
VGEN, SB3_NB/2, ALL, , , , SB3_DIST, , , 0

NUMCMP, ALL

!建立芯片下凸点及芯片模型
WPOFF, SB1_DIST/2, SB1_DIST/2, SUB_HEIGHT+SB1_HEIGHT/2
SPHERE, SB1_RADIUS, , 0, 360
WPOFF, -SB1_DIST/2, -SB1_DIST/2, SB1_HEIGHT/2
BLOCK, 0, D1_LENGTH/2, 0, D1_WIDTH/2, 0, D1_HEIGHT
BLOCK, 0, D2_LENGTH/2, D_DIST-D2_WIDTH/2, D_DIST+D2_WIDTH/2, 0, D2_HEIGHT
BLOCK, D_DIST-D2_LENGTH/2, D_DIST+D2_LENGTH/2, 0, D2_WIDTH/2, 0, D2_HEIGHT
WPOFF, D_DIST-D2_LENGTH/2+SB2_SIDE, SB2_DIST/2, -SB2_HEIGHT/2
SPHERE, SB2_RADIUS, , 0, 360
WPOFF, -(D_DIST-D2_LENGTH/2+SB2_SIDE), -SB2_DIST/2
WPOFF, SB2_DIST/2, D_DIST-D2_WIDTH/2+SB2_SIDE
SPHERE, SB2_RADIUS, , 0, 360
WPOFF, -SB2_DIST/2, -(D_DIST-D2_WIDTH/2+SB2_SIDE), SB2_HEIGHT/2
VSEL, S, LOC, Z, -(SB1_HEIGHT+SUB_HEIGHT), D1_HEIGHT
VOVLAP, ALL
NUMCMP, ALL
VSEL, S, LOC, Z, -(SB1_HEIGHT+SUB_HEIGHT), -SB1_HEIGHT
VADD, ALL
NUMCMP, ALL
VSEL, S, LOC, Z, 0, D1_HEIGHT
VADD, ALL
NUMCMP, ALL

VSEL, S, LOC, X, 0, D1_LENGTH/2
VSEL, R, LOC, Y, 0, D1_WIDTH/2
VSEL, R, LOC, Z, 0, -SB1_HEIGHT
VGEN, SB1_NB/2, ALL, , , , SB1_DIST, , , 0

VSEL, S, LOC, X, 0, D1_LENGTH/2
VSEL, R, LOC, Y, 0, D1_WIDTH/2
VSEL, R, LOC, Z, 0, -SB1_HEIGHT
VGEN, SB1_NB/2, ALL, , , SB1_DIST, , , , 0

VSEL, S, LOC, X, D_DIST-D2_LENGTH/2, D_DIST+D2_LENGTH/2
VSEL, R, LOC, Y, 0, D2_WIDTH/2
VSEL, R, LOC, Z, 0, -SB2_HEIGHT
VGEN, SB2_NB, ALL, , , SB2_DIST, , , , 0

VSEL, S, LOC, X, D_DIST-D2_LENGTH/2, D_DIST+D2_LENGTH/2
VSEL, R, LOC, Y, 0, D2_WIDTH/2
VSEL, R, LOC, Z, 0, -SB2_HEIGHT
VGEN, SB2_NB/2, ALL, , , , SB2_DIST, , , 0

VSEL, S, LOC, X, 0, D2_LENGTH/2
VSEL, R, LOC, Y, D_DIST-D2_WIDTH/2, D_DIST+D2_WIDTH/2
VSEL, R, LOC, Z, 0, -SB2_HEIGHT
VGEN, SB2_NB/2, ALL, , , SB2_DIST, , , , 0

VSEL, S, LOC, X, 0, D2_LENGTH/2
VSEL, R, LOC, Y, D_DIST-D2_WIDTH/2, D_DIST+D2_WIDTH/2
VSEL, R, LOC, Z, 0, -SB2_HEIGHT
VGEN, SB2_NB, ALL, , , , SB2_DIST, , , 0

!建立芯片上热介质材料模型
WPOFF, 0, 0, D1_HEIGHT
BLOCK, 0, D1_LENGTH/2, 0, D1_WIDTH/2, 0, TIM_HEIGHT
BLOCK, 0, D2_LENGTH/2, D_DIST-D2_WIDTH/2, D_DIST+D2_WIDTH/2, 0, TIM_HEIGHT
BLOCK, D_DIST-D2_LENGTH/2, D_DIST+D2_LENGTH/2, 0, D2_WIDTH/2, 0, TIM_HEIGHT

!建立扩展面模型
WPOFF, 0, 0, TIM_HEIGHT
BLOCK, 0, HS_LENGTH/2, 0, HS_WIDTH/2, 0, HS_THICK
*SET, HS_HEIGHT, TIM_HEIGHT+D1_HEIGHT+SB1_HEIGHT-SA_HEIGHT
BLOCK, 0, SUB_LENGTH/2, SUB_WIDTH/2-HS_THICK, SUB_WIDTH/2, 0, -HS_HEIGHT
BLOCK, SUB_LENGTH/2-HS_THICK, SUB_LENGTH/2, 0, SUB_WIDTH/2-HS_THICK, 0, -HS_HEIGHT

!建立基板上粘接剂模型
WPOFF, 0, 0, -(TIM_HEIGHT+D1_HEIGHT+SB1_HEIGHT)
BLOCK, 0, SUB_LENGTH/2, SUB_WIDTH/2-HS_THICK, SUB_WIDTH/2, 0, SA_HEIGHT
BLOCK, SUB_LENGTH/2-HS_THICK, SUB_LENGTH/2, 0, SUB_WIDTH/2-HS_THICK, 0, SA_HEIGHT

!建立热沉模型
WPOFF, 0, 0, TIM_HEIGHT+D1_HEIGHT+SB1_HEIGHT+HS_THICK
BLOCK, 0, SUB_LENGTH/2, 0, SUB_WIDTH/2, 0, TIM_HEIGHT
BLOCK, 0, SINK_LENGTH/2, 0, SINK_WIDTH/2, TIM_HEIGHT, TIM_HEIGHT+SINK_HEIGHT

WPOFF, 0, 0, TIM_HEIGHT+SINK_HEIGHT
BLOCK, SINK_LENGTH/2-FIN_THICK, SINK_LENGTH/2, 0, SINK_WIDTH/2, 0, FIN_HEIGHT
VSEL, S, LOC, Z, 0, FIN_HEIGHT
VGEN, FIN_NB/2, ALL, , , -(FIN_DIST+FIN_THICK), , , , 0

!通过OVERLA将PCB分为两部分，方便结构规则部分进行SWEEP网格划分
CSYS, 0
WPAVE, 0, 0, 0
CSYS, 4
BLOCK, 0, SUB_LENGTH/2, 0, SUB_WIDTH/2, 0, PCB_HEIGHT
VSEL, S, LOC, Z, 0, PCB_HEIGHT
VOVLAP, ALL
NUMCMP, ALL

!全部体积通过VGLUE粘合在一起
VSEL, ALL
VGLUE, ALL

liaojing500

我也遇到过一种可能，在执行glue命令时你计算机内存不够了，算不出来（特别是bump和solder ball很多的）。我换了台机子，或者减小模型复杂度就好了。

榆树湾

走了一波，没问题啊